1. Field
Example embodiments relate to semiconductor discrete devices, semiconductor integrated circuit interconnections and methods of forming the same. Other example embodiments relate to transistors, semiconductor integrated circuit interconnections and methods of forming the same.
2. Description of Related Art
Transistors or semiconductor integrated circuit interconnections have been recently formed by burying a conductive layer in a trench defined by a material layer according to a gradual reduction of a design rule. The conductive layer may be formed into a buried gate of a transistor or a buried interconnection of a semiconductor integrated circuit interconnection. The material layer may be a semiconductor substrate or an insulating layer on the semiconductor substrate. The buried gate or the buried interconnection may increase the volume thereof in the trench, thereby improving a current driving capability of the transistor or a current transmission capability of the semiconductor integrated circuit interconnection.
However, the buried gate or the buried interconnection makes it difficult to perform a semiconductor fabrication process related to the transistor or the semiconductor integrated circuit interconnection. The residue of the conductive layer may be formed on the material layer during an etching process due to a step difference between a bottom surface of the trench and an upper surface of the material layer while the buried gate or buried interconnection is formed. The buried gate or buried interconnection may be electrically connected to another buried gate or another buried interconnection around the trench through the residue of the conductive layer.
The buried gate constitutes a transistor with electrical nodes and diffusion regions. The electrical nodes may be disposed around the buried gate and contact the diffusion regions. The electrical nodes may contact the buried gate due to gradually reducing the design rule. The electrical nodes may electrically short-circuit the buried gate and diffusion regions.
The conventional buried gate discloses an active region that is defined in a semiconductor substrate. A trench may be formed in the active region, a buried gate may be formed in the trench, and electrical nodes may be formed on the buried gate and the active regions around the buried gate. However, the buried gate may easily contact the electrical nodes of the active regions due to gradually reducing the design rule.